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Hello Lustre developers and maintainers,</div>
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<br>
</div>
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I am writing to inquire about any existing plans to support the RISC-V</div>
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architecture in future Lustre releases, and to share our work on enabling</div>
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Lustre client functionality on RISC-V 64-bit systems.</div>
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<br>
<br>
</div>
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BACKGROUND: WHY RISC-V SUPPORT MATTERS FOR LUSTRE</div>
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<b>-------------------------------------------------</b></div>
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<br>
</div>
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RISC-V is gaining significant momentum in the HPC community, with projects</div>
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like the European Processor Initiative (EPI), EPAC, and commercial offerings</div>
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from SiFive targeting high-performance computing workloads. However, a</div>
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critical gap exists in the RISC-V HPC ecosystem: there is currently no</div>
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high-performance parallel file system support for RISC-V.</div>
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<br>
</div>
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This gap has been formally identified in the RISC-V HPC Gap Analysis by</div>
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Nick Brown [1], which explicitly recommends:</div>
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<br>
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"We should prioritise optimisation of parallel filesystems,</div>
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including Lustre, for RISC-V"</div>
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<br>
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Adding RISC-V support to Lustre would:</div>
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<br>
</div>
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1. Signal RISC-V readiness for production HPC - Lustre is the de facto</div>
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standard for HPC storage, powering ~70% of TOP500 systems</div>
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<br>
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2. Align with open-source values - Both Lustre and RISC-V share a</div>
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commitment to open-source collaboration</div>
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<br>
</div>
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3. Enable new deployment scenarios - RISC-V-based compute nodes</div>
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connecting to existing Lustre infrastructure</div>
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<br>
<br>
</div>
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OUR WORK: LUSTRE 2.17.0 ON RISC-V</div>
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<b>---------------------------------</b></div>
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<br>
</div>
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We have successfully built and tested the Lustre 2.17.0 client on RISC-V</div>
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64-bit with a minimal set of patches. This work demonstrates that Lustre</div>
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can be ported to RISC-V with relatively low effort, as also shown in</div>
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recent academic work by Billa et al. at SCA/HPCAsiaWS '26 [2].</div>
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<br>
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Patch Summary:</div>
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<br>
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Our patch series consists of 8 small patches targeting:</div>
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<br>
</div>
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- Build system: RISC-V SUBARCH mapping in autoconf</div>
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- RPM/DKMS: Architecture-agnostic paths</div>
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- LNet: RISC-V hypervisor detection handling</div>
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- llite: Guard for prefetchw() (x86-specific instruction)</div>
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- Erasure coding: Enable optimized paths for RISC-V</div>
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- Debug tools: RISC-V target in crash tools</div>
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<br>
</div>
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Total impact: 9 files changed, 19 insertions(+), 8 deletions(-)</div>
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<br>
</div>
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Test Environment:</div>
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<br>
</div>
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- Primary: Ubuntu 24.04 RISC-V, Linux kernel 6.8.4</div>
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- Validation: Fedora 42 x86_64, Linux kernel 6.16.4</div>
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- Result: All 16 client kernel modules compile and load successfully</div>
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<br>
<br>
</div>
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QUESTIONS FOR THE COMMUNITY</div>
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<b>---------------------------</b></div>
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<br>
</div>
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1. Are there any existing plans or ongoing efforts to add RISC-V</div>
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support to Lustre?</div>
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<br>
</div>
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2. Would the maintainers be interested in reviewing our patch series</div>
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for potential inclusion?</div>
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<br>
</div>
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3. Are there specific testing requirements or coding standards we</div>
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should address before formal submission?</div>
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<br>
<br>
</div>
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NEXT STEPS</div>
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<b>----------</b></div>
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<br>
</div>
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We are prepared to:</div>
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<br>
</div>
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- Submit the patches via Gerrit for formal review</div>
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- Create a Jira ticket to track this feature request</div>
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- Provide additional testing data as needed</div>
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- Collaborate with maintainers on any required changes</div>
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<br>
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The patches are available in our repository and we can submit them in</div>
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whatever format is most convenient for the review process.</div>
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<br>
<br>
</div>
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REFERENCES</div>
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<b>----------</b></div>
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<br>
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[1] Nick Brown, "RISC-V HPC Gap Analysis", RISC-V International, Oct 2025</div>
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<a style="margin: 0px;" data-linkindex="0" title="https://riscv.atlassian.net/wiki/spaces/OLRR/pages/895778831/HPC+Gap+analysis" class="ms-outlook-linkify OWAAutoLink" id="OWAb5b0d5de-4950-559d-e301-5124963f5dcb" target="_blank" href="https://riscv.atlassian.net/wiki/spaces/OLRR/pages/895778831/HPC+Gap+analysis">https://riscv.atlassian.net/wiki/spaces/OLRR/pages/895778831/HPC+Gap+analysis</a></div>
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[2] Surendra Billa et al., "Porting Lustre File System to RISC-V</div>
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Architecture", SCA/HPCAsiaWS '26, ACM</div>
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<a style="margin: 0px;" data-linkindex="1" title="https://dl.acm.org/doi/10.1145/3784828.3785406" class="ms-outlook-linkify OWAAutoLink" id="OWAfd028089-0d6e-e236-6ddf-7eb585f77c10" target="_blank" href="https://dl.acm.org/doi/10.1145/3784828.3785406">https://dl.acm.org/doi/10.1145/3784828.3785406</a></div>
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Thank you for your time and consideration. We look forward to your</div>
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feedback and the opportunity to contribute to Lustre's architecture</div>
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support.</div>
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Best regards,</div>
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Abdul Halim</div>
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OpenChip</div>
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abdul.halim@openchip.com</div>
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