[lustre-devel] [RFC] RISC-V Architecture Support for Lustre - Patch Series Available

[Abdul Halim | OPENCHIP]

Hello Lustre developers and maintainers,

I am writing to inquire about any existing plans to support the RISC-V
architecture in future Lustre releases, and to share our work on enabling
Lustre client functionality on RISC-V 64-bit systems.


BACKGROUND: WHY RISC-V SUPPORT MATTERS FOR LUSTRE
-------------------------------------------------

RISC-V is gaining significant momentum in the HPC community, with projects
like the European Processor Initiative (EPI), EPAC, and commercial offerings
from SiFive targeting high-performance computing workloads. However, a
critical gap exists in the RISC-V HPC ecosystem: there is currently no
high-performance parallel file system support for RISC-V.

This gap has been formally identified in the RISC-V HPC Gap Analysis by
Nick Brown [1], which explicitly recommends:

    "We should prioritise optimisation of parallel filesystems,
     including Lustre, for RISC-V"

Adding RISC-V support to Lustre would:

  1. Signal RISC-V readiness for production HPC - Lustre is the de facto
     standard for HPC storage, powering ~70% of TOP500 systems

  2. Align with open-source values - Both Lustre and RISC-V share a
     commitment to open-source collaboration

  3. Enable new deployment scenarios - RISC-V-based compute nodes
     connecting to existing Lustre infrastructure


OUR WORK: LUSTRE 2.17.0 ON RISC-V
---------------------------------

We have successfully built and tested the Lustre 2.17.0 client on RISC-V
64-bit with a minimal set of patches. This work demonstrates that Lustre
can be ported to RISC-V with relatively low effort, as also shown in
recent academic work by Billa et al. at SCA/HPCAsiaWS '26 [2].

Patch Summary:

Our patch series consists of 8 small patches targeting:

  - Build system:      RISC-V SUBARCH mapping in autoconf
  - RPM/DKMS:          Architecture-agnostic paths
  - LNet:              RISC-V hypervisor detection handling
  - llite:             Guard for prefetchw() (x86-specific instruction)
  - Erasure coding:    Enable optimized paths for RISC-V
  - Debug tools:       RISC-V target in crash tools

Total impact: 9 files changed, 19 insertions(+), 8 deletions(-)

Test Environment:

  - Primary:    Ubuntu 24.04 RISC-V, Linux kernel 6.8.4
  - Validation: Fedora 42 x86_64, Linux kernel 6.16.4
  - Result:     All 16 client kernel modules compile and load successfully


QUESTIONS FOR THE COMMUNITY
---------------------------

  1. Are there any existing plans or ongoing efforts to add RISC-V
     support to Lustre?

  2. Would the maintainers be interested in reviewing our patch series
     for potential inclusion?

  3. Are there specific testing requirements or coding standards we
     should address before formal submission?


NEXT STEPS
----------

We are prepared to:

  - Submit the patches via Gerrit for formal review
  - Create a Jira ticket to track this feature request
  - Provide additional testing data as needed
  - Collaborate with maintainers on any required changes

The patches are available in our repository and we can submit them in
whatever format is most convenient for the review process.


REFERENCES
----------

[1] Nick Brown, "RISC-V HPC Gap Analysis", RISC-V International, Oct 2025
    https://riscv.atlassian.net/wiki/spaces/OLRR/pages/895778831/HPC+Gap+analysis

[2] Surendra Billa et al., "Porting Lustre File System to RISC-V
    Architecture", SCA/HPCAsiaWS '26, ACM
    https://dl.acm.org/doi/10.1145/3784828.3785406


Thank you for your time and consideration. We look forward to your
feedback and the opportunity to contribute to Lustre's architecture
support.

Best regards,

Abdul Halim
OpenChip
abdul.halim at openchip.com




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